1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, in particular, a semiconductor device wherein a capacitative section and transistor section are provided on the same substrate.
2. Description of the Related Art
Previously, semiconductor devices in which capacitative sections and transistor sections were provided on the same substrate, for example capacitative section peripheral portions of devices used in CMOS logic ICs were manufactured by a method as below. A brief description is given below with reference to FIG. 7.
First of all, the upper surface of substrate 101 is oxidised to form a thin SiO.sub.2 film (not shown); an active region 107 is then produced by forming a thick field oxide film 105 to effect element isolation. The thin SiO.sub.2 film on substrate 101 is then removed (FIG. 7(A)).
Next, a thin SiO.sub.2 film 103 is formed by again oxidising the upper surface of substrate 101. On this SiO.sub.2 film 103 and on field oxide film 105, a polycrystalline Si layer 109 (lower electrode polysilicon film) for the lower electrode of the capacitative section is deposited, and a dielectric film 111 is formed on this lower electrode polysilicon layer 109. Next, a mask 113 is formed corresponding to the shape of the lower electrode of the capacitative section (FIG. 7(B)).
Using this mask 113, photolithography and subsequent etching processing are performed, so as to leave behind only the polysilicon 109a and dielectric film 11a in the region on field oxide film 105 where the capacitative section is subsequently to be formed (FIG. 7(C)).
At this point, the thin SiO.sub.2 film 103 is also removed. Gate oxide film 115a is then formed on active region 107 by again performing oxidation. Also, oxide film 115b is formed on the side face of lower electrode polysilicon 109a. Next, a polysilicon layer 117 for the gate electrode and upper electrode is deposited on the entire upper surface of this structure and furthermore a WSi.sub.x layer 119 (tungsten silicide) is deposited on this polysilicon layer 117. This polysilicon layer 117 and WSi.sub.x layer 119 (x indicates the composition ratio and has a value in the range 2.2&lt;x&lt;2.5) are of gate electrode material, or the material of the upper electrode of the capacitative section could also be used. After this, a resist pattern 121 of the shape of the upper electrode and gate electrode is formed on WSi.sub.x 119 (FIG. 7(D)).
By performing photolithography and etching, an upper electrode layer 123 consisting of part 117a of polysilicon 117 and part 119a of WSi.sub.x 119 is formed on dielectric film 111a, and a gate electrode 125 consisting of part 117b of the polysilicon and part 119b of the WSi.sub.x is formed on gate oxide film 115a (FIG. 7(E))
As described above, the upper electrode of the capacitative section is constituted by polysilicon and tungsten silicide. It is desirable that the concentration of the phosphorus, which is an impurity in the polysilicon of the upper electrode and lower electrode of the capacitative section, should be the same, but if the upper electrode is formed of the same material in the same step as the gate electrode of the transistor, the polysilicon of the upper electrode contains phosphorus in a concentration of for example 4.times.10.sup.20 ion/cm.sup.3. In contrast, the polysilicon of the lower electrode contains phosphorus in a concentration of 6.times.10.sup.20 ion/cm.sup.3, so there is a difference in the phosphorus concentrations. Furthermore, the phosphorus that is contained in the polysilicon of this upper electrode diffuses into the tungsten silicide under subsequent heat treatment. This therefore further reduces the phosphorus concentration in the polysilicon of the upper electrode, increasing the difference in concentration of silicon between the upper electrode and lower electrode.
As a result, with the dispersion of phosphorus ions (P.sup.+) into the WSi.sub.x, electron migration takes place, turning the vicinity of the interface between the dielectric film and lower electrode into a depletion layer. This therefore gives rise to the problem of change in the capacitance of the capacitative section dependent on voltage.
It is therefore necessary to eliminate the difference in phosphorus concentration of the upper electrode and lower electrode by raising the phosphorus concentration in the upper electrode of the capacitative section.
Accordingly, the method has of course been considered of, when forming the upper electrode, forming this using a material wherein the phosphorus concentration of the polysilicon is raised beforehand and then depositing the tungsten silicide; however, it has been confirmed by experiment etc. that, if this is done, adhesion between the polysilicon and tungsten silicide is poor.
Realisation of a method of forming a capacitative section of a semiconductor device whereby the phosphorus concentration of the upper electrode could be raised to the same level as the phosphorus concentration of the lower electrode without loss of adhesion between the polysilicon and tungsten silicide was therefore desired.